The present invention relates to an information processor such as a personal computer or a work station, and more particularly to an information processing system in which a plurality of internal buses are hierarchically connected through a bus adaptor or bus converter.
The prior art concerning a computer system including a plurality of internal buses hierarchically connected through a bus adaptor (or bus converter) has been disclosed in JP-A-5-233528.
In the prior art, it is generally known that in order to prevent the transfer by a low-speed I/O module from disturbing the transfer for a low-speed processor memory, independent buses including a processor bus, a system bus and an I/O bus are hierarchically connected to configure a system. The adjacent buses are connected by a bus adaptor (or bus converter). In a general information processor, it is generally known that the protocols of connected buses are different. Therefore, a protocol conversion processing is performed in the bus converter.
In the case where an application handling multimedia, especially, moving images is performed by an information processor such as a personal computer, the handling of a large amount of data may cause the case where the supply of data to be processed from the I/O side to a CPU or a main memory is not in time due to an overhead time for protocol conversion resulting from the hierarchization of buses. On the other hand, in the case where data processed by the CPU or the main memory is to be transferred to a display unit provided on the I/O bus side, there is also a possibility that the display at a fixed transfer rate becomes impossible. When a processing such as the compression/decompression of a moving image is taken into consideration, it may further be considered that the processing capacity of the CPU itself is insufficient even if the supply of data from the I/O side is in time.